As it is well known, a reading operation of a flash memory cell comprised in a large flash memory requires a reading current passing through the cell to be compared with a current, called a reference current, so as to determine if the read cell is a logic “1” or “0”.
In particular, if the cell reading current is higher than the reference current, the digital value allocated to the read cell is 1; if the reading current is lower than the reference current, the digital value allocated to the read cell is 0.
The so-obtained digital value is thus the information stored in the read cell.
It is also known that in traditional flash memories the reference current value is obtained by means of a flash memory cell, called reference cell, which is programmed so as to have a reading current value being median between the reading current values of a programmed cell and of an erased cell.
This mean reading current value is transferred by means of a current mirror to all reading comparators or sense amplifiers in a memory cell reading device associated with the flash memory. The mean reading current value is particularly used as a decision threshold by the sense amplifier to determine the digital value stored in the read cells, as shown in FIG. 1.
In particular, this figure schematically shows a portion 10 of a flash memory architecture comprising a sense amplifier 11 connected to a memory cell 12 of a memory matrix 1, this cell 12 corresponding to a selected bitline 2 and wordline 3 and being also indicated as matrix cell.
The sense amplifier 11 is also connected, through a current mirror 13, to a reference cell 14, of the flash type, having in turn a control terminal connected to a reference wordline 15. In particular, the current mirror 13 comprises a first mirror transistor M1 connected to the reference cell 14 as well as a plurality of second mirror transistors Mn connected to each one of the sense amplifiers 11 being provided in the flash memory. The first mirror transistor M1 is connected through a line Ref_mirror to the plurality of sense amplifiers 11.
As seen, the sense amplifier 11 compares a value of a reference current Iref provided by the reference cell 14 with a value of a cell current Icell passing through the selected matrix cell 12, and it provides on an output terminal OUT of the sense amplifier 11 a digital value corresponding to the content of the matrix cell 12.
It is worth noting that the use of a flash reference cell for generating the reference current ensures a same dependence with respect to process, temperature and supply voltage changes of the reference current and the cell current.
In the case of high density flash memories, the reference current distribution along the whole memory cell matrix causes problems linked to parasitic effects. In fact, the sole line Ref_mirror is connected to a large number of sense amplifiers concerning it. The number of these sense amplifiers 11 is further increased in recent construction flash memories to meet speed requirements needed by burst reading operations and to perform simultaneous writing and reading operations.
Moreover, with large memory devices, the physical path of the line Ref_mirror is very long.
These two conditions both produce a high capacitance value in a connection node XRF between the first mirror transistor M1 and the plurality of second mirror transistors Mn in sense amplifiers 11, and thus a high sensitivity to couplings and noises in the flash memory device, as shown in FIG. 2.
In particular, this FIG. 2 shows these undesired effects, i.e., the high capacitance value 21 in the node XRF, the high sensitivity to couplings 22 and noises 23.
In such conditions, couplings with variable signals, such as a clock signal and the signal on a data bus associated with the memory device, as well as noises caused by local changes of a supply voltage and mainly the high parasitic capacitance caused by the signal path length in big-sized devices, such as the conductive paths between the reference cell and sense amplifiers, may cause a reading error which results from the sense amplifiers reading with an actual reference current different from the theoretical current.
The line Ref_mirror is an analog line and thus very sensitive to couplings and noise on a memory device supply line.
In other words, memory devices using a single reference cell reading architecture, as the one shown in FIG. 1, have a safety margin for reading operations performed on their cells being lower than the desired margin and they can even have reading errors.
Another aspect to be considered is that the reference cell consumes currents during its operation and, is thus turned off when the memory device is in a stand-by condition.
When a reading is performed after a stand-by period, it is thus necessary to reactivate the line Ref_mirror since only after this reactivation a reading operation can be performed on matrix cells.
The reactivation operation is however obstructed by the high parasitic load associated with the node XRF.
To overcome these drawbacks it is known to equip memory devices comprising single reference cell reading architectures with accurate precharging, buffering and shielding circuits for reference lines concerning sense amplifiers associated with matrix cells.
In reality, these memory devices are, however, very sensitive to noise and to sudden local supply increases.
Moreover, the time required to set these common or global reference lines is a limiting factor for the device performances during reading operations.
It is also known to use a plurality of local reference cells associated with sense amplifiers. In this case, however, accurate testing operations to set uniformly the reference level must typically be provided. Problems linked to the time needed to perform these tests thus arise, as well as evident problems linked to the area occupation of the reading architecture and thus of the whole memory device.